1. Field of the Invention
This invention relates to a MOS type semiconductor integrated circuit device having a protection device against static electricity applied to the input or output terminal, or input/output terminal of the circuit.
2. Description of the Related Art
A MOS type semiconductor integrated circuit device incorporates a protection circuit to protect itself from the static electricity applied to its external input or output terminal or input/output terminal (hereinafter called "I/O terminal"). Most protection circuit of this type comprises elements which perform bipolar operation when the static electricity is applied, as is disclosed in, for example, U.S. Pat. No. 4,734,752.
FIGS. 7-9 show protection elements which perform bipolar operation.
In FIG. 7, an I/O terminal 1 is connected to an inverter circuit IV by a resistor R. The inverter circuit IV includes transistors 21 and 22. The I/O terminal is also connected to the drains of a P-channel MOS transistor 2 and an N-channel MOS transistor 3. The sources of the transistors 2 and 3 are connected to the gates thereof, and also to source voltages V.sub.DD and V.sub.SS, respectively. These transistors 2 and 3 form an input protection circuit.
The circuit shown in FIG. 8 is identical to that shown in FIG. 7, except that it further includes transistors 4 and 5. The transistors 4 and 5 have drains connected to the I/O terminal 1, sources connected to the source voltages V.sub.DD and V.sub.SS, respectively, and gates connected to internal circuits (not shown). This is an input/output circuit responsive to a signal supplied from the internal circuit.
FIG. 9 shows an input protection circuit which differs from the circuit shown in FIG. 7 in that it further incorporates a pull-down N-channel MOS transistor 6. The transistor 6 has a drain and a source connected to the I/O terminal 1 and source voltage V.sub.SS, respectively.
The N-channel MOS transistors incorporated in the circuits shown in FIGS. 7-9 have, for example, LDD (Lightly Doped Drain) structure, and their characteristics are not deteriorated by hot carriers.
FIG. 10 is a cross section showing a transistor 7 corresponding to the transistors 3, 5, and 6 shown in FIGS. 7-9, and a transistor 8 corresponding to the transistor 22. The transistors 7 and 8 have the LDD structure and a channel length L.sub.2 determined by the ordinal refining technique.
The transistor 8 has low density diffusion regions L.sub.DDN -. To enhance the reliability of the transistor 8 and to make it applicable to various source voltages, the impurity density (or "dose amount") of the low density diffusion regions is set at Q.sub.2 (3.times.10.sup.18 cm.sup.-3), so that the substrate current Isub assumes a minimum value as is shown in FIG. 11.
However, if the transistor 7 which forms a protection circuit is replaced with the transistor 8 used as an internal transistor not connected to the I/O terminal 1, a sufficient electrostatic breakdown voltage cannot be obtained, as is indicated by Q.sub.2 in FIG. 12.
To increase the electrostatic breakdown voltage, the conventional device has transistors having large channel widths, and inevitably has a large size. The device is not suitable for high integration.